1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and is particularly suitably applied to a latch circuit or a flip-flop circuit that operates in synchronization with a clock signal.
2. Description of the Related Art
In a conventional flip-flop circuit, for example, data transfer and hold is performed by operating a clocked inverter by a clock signal and a clock inverted signal (Japanese Patent Application Laid-open No. S62-40816).
However, a clock buffer that generates the clock inverted signal from the clock signal is additionally needed, and power is consumed in the clock buffer at every clock transition, so that the power consumption increases by that amount. Specially, in the case of a low switching rate at which the output does not change even when being triggered by the clock, the power consumption in the clock buffer is wasteful.